The etchback approach: Enlarged process window for MuGFET gate etching

Microelectronic Engineering

Volumn 83, Issue 3, 2006, Pages 570-576

  Degroote, Bart ^a   Collaert, Nadine ^a   Rooyackers, Rita ^a   Baklanov, Mikhail R ^a   Boullart, Werner ^a   Kunnen, Eddy ^a   Jurczak, Malgorzata ^a   Vanhaelemeersch, Serge ^a  

^a IMEC   (Belgium)

Author keywords

Anisotropic etchback; Dry etching; Gate etch; Multiple gate FET; Topography

Indexed keywords

ANISOTROPY; DRY ETCHING; FIELD EFFECT TRANSISTORS; PROCESS CONTROL; SURFACE TOPOGRAPHY; THIN FILMS;

ANISOTROPIC ETCHBACK; GATE ETCH; MULTIPLE-GATE FET; TOPOGRAPHY;

GATES (TRANSISTOR);

EID: 33244463504     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2005.12.015     Document Type: Article

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