CMOS evolution. Development limits

Materials Science- Poland

Volumn 26, Issue 1, 2008, Pages 5-20

  Jakubowski, A ^a   LUkasiak L ^a  

^a WARSAW UNIVERSITY OF TECHNOLOGY   (Poland)

Author keywords

CMOS; Scaling; Silicon microelectronics; Silicon on insulator; SOI; Strained silicon

Indexed keywords

CHARGE COUPLED DEVICES; ELECTRIC CONDUCTIVITY; LOGIC CIRCUITS; MICROELECTRONICS; MOS DEVICES; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR MATERIALS; TRANSISTOR TRANSISTOR LOGIC CIRCUITS; TRANSISTORS;

COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) TECHNOLOGY; EVOLUTION (CO); FUNDAMENTAL LIMITATIONS; MOS TRANSISTORS; NEW OPTIONS; SILICON MICROELECTRONICS; SOI TECHNOLOGY; STRAIN ENGINEERING;

SEMICONDUCTOR DEVICES;

EID: 45849151746     PISSN: 01371339     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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