Model-based mask verification on critical 45nm logic masks

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 7028, Issue , 2008, Pages

  Sundermann, F ^a   Foussadier, F ^a   Takigawa, T ^b   Wiley, J ^b   Vacca, A ^b   Depre, L ^b   Chen, G ^b   Bai, S ^b   Wang, J S ^b   Howell, R ^b   Arnoux, V ^b   Hayano, K ^c   Narukawa, S ^c   Kawashima, S ^c   Mohri, H ^c   Hayashi, N ^c   Miyashita, H ^c   Trouiller, Y ^d   Robert, F ^a   Vautrin, F ^a   Kerrien, G ^a   Planchot, J ^a   Martinelli, C ^a   Di Maria, J L ^d   Farys, V ^a   Vandewalle, B ^a   Perraud, L ^d   Le Denmat, J C ^a   Villaret, A ^a   Gardin, C ^a   Yesilada, E ^a   Saied, M ^a   more..

^a STMICROELECTRONICS   (France)

^b Brion Technologies   (United States)

^c DAI NIPPON PRINTING CO LTD   (Japan)

^d CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CADMIUM; CADMIUM COMPOUNDS; COMPUTER NETWORKS; CRACK DETECTION; DATA STORAGE EQUIPMENT; FUZZY LOGIC; MAPS; MASKS; MICROFLUIDICS; MODAL ANALYSIS; PHOTOACOUSTIC EFFECT; PHOTORESISTS; TECHNOLOGY;

BRION TECHNOLOGIES (CO); CD UNIFORMITY (CDU); CRITICAL DIMENSION UNIFORMITY (CDU); ERROR BUDGETING; HOT SPOTTING; HOT-SPOTS; INDIVIDUAL (PSS 544-7); MAP GENERATION; MASK CD UNIFORMITY; MASK ERRORS; MASK PROCESSES; MASK TECHNOLOGY; MODEL BASED (OPC); NEXT-GENERATION LITHOGRAPHY (NGL); OPTICAL (PET) (OPET); PHOTO MASKING; PROCESS SIMULATIONS; RESIST MODELS; SCANNING ELECTRON MICROSCOPY (SEM) IMAGES;

DYNAMIC MODELS;

EID: 45549093324     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.793037     Document Type: Conference Paper

References (4)

1. Franck Foussadier, Frank Sundermann, Anthony Vacca, et al, "Model-Based Mask Verification," Proc. of SPIE Vol. 6730, November 2007.
2. Peter Buck et al, "Methods for Analyzing and Compensating for Systematic Mask CD errors," Solid State Technology, December 2006.
3. Masaki Satake et al, "Evaluation of Lithography Simulation Model Accuracy for Hot Spot-based Mask Quality Assurance," Proc. of SPIE Vol. 6607, 66071E, 2007.
4. Bertrand LeGratiet et al, "Process Control for 45nm CMOS Logic Gate Patterning," Proc. of SPIE Vol. 6922-33 Feb 2008.