A 20Gb/s 0.13um CMOS serial link transmitter using an LC-PLL to directly drive the output multiplexer

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2004, Pages 272-275

  Chiang, Patrick ^a   Daily, William J ^a,b   Lee, Ming Ju Edward ^c   Senthinathan, Ramesh ^c   Oh, Yangjin ^a   Horowitz, Mark ^a  

^a STANFORD UNIVERSITY   (United States)

^b Velio Communications   (United States)

^c ATI Technologies   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CAPACITANCE; ELECTRIC POTENTIAL; ENERGY UTILIZATION; JITTER; MULTIPLEXING; PHASE LOCKED LOOPS; POWER SUPPLY CIRCUITS; SAMPLING; TRANSMITTERS; VARIABLE FREQUENCY OSCILLATORS;

DIGITAL LOGIC; MULTIPLEXERS; POWER CONSUMPTION; STATIC PHASE;

CMOS INTEGRATED CIRCUITS;

EID: 4544355582     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. C.-K. Yang and M. Horowitz. "A 0.8um CMOS 2.5Gb/s oversampling receiver and transmitter for serial links." IEEE Journal of Solid-State Circuits, December 1996, Vol. 31, No. 12, pp. 2015-2023.
2. M.-J. E. Lee, W. J. Dally, P. Chiang. "Low-Power Area-Efficient High-Speed I/O Circuit Techniques." IEEE Journal of Solid-State Circuits, November 2000, Vol. 35, No. 11, pp. 1591-1599.
3. J. Cao, et. al. "OC-192 Transmitter and Receiver in standard 0.18-/spl mu/m CMOS." IEEE Journal of Solid-State Circuits, December 2002, Vol. 37, No. 12, pp. 1768-1780.
4. L. Henrickson, et. al. "Low-Power Fully Integrated 10-Gb/s SONET/ SDH Transceiver in 0.13-um CMOS." IEEE Journal of Solid-State Circuits, October 2003, Vol. 38, No. 10, pp. 1595-1601.
5. W. Ellersick, et. al. "A Serial-Link Transceiver Based on 8 Gsample/s A/D and D/A Converters in 0.25um CMOS", ISSCC Dig. Of Tech. Papers, pp. 58-59, Feb. 2003.