A serial-link transceiver based on 8GSample/s A/D and D/A converters in 0.25μm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 58-59+430

  Ellersick, W ^a   Yang, C K K ^a   Stojanovic, V ^a   Modjtahed, S ^a   Horowitz, M A ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; DIGITAL TO ANALOG CONVERSION; ELECTRIC CLOCKS; ELECTRIC INDUCTORS; PHASE LOCKED LOOPS; TIMING CIRCUITS;

SERIAL-LINK TRANSCIEVERS;

TRANSCEIVERS;

EID: 0035054765     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. A 2Gb/s/pin CMOS asymmetric serial link
2. A 0.5-μm CMOS 4.0-Gb/s serial link transceiver with data recovery using oversampling
3. GAD: A 12-GS/s CMOS 4-bit ADC for an equalized multi-level link
4. Monolithic CMOS distributed amplifier and oscillator