Design and fabrication of high aspect ratio fine pitch interconnects for wafer level packaging

Proceedings of 4th Electronics Packaging Technology Conference, EPTC 2002

Volumn , Issue , 2002, Pages 229-234

  Aggarwal, A O ^a   Markondeya Raj, P ^a   Pratap, R J ^a   Saxena, A ^a   Tummala, R R ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASPECT RATIO; COST EFFECTIVENESS; FABRICATION; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUIT INTERCONNECTS; SELF ASSEMBLY;

COMPLIANT INTERCONNECTS; COPPER INTERCONNECTS; ELECTRICAL AND MECHANICAL PROPERTIES; ELECTRONIC PACKAGING; FINE PITCH INTERCONNECTS; MECHANICAL REQUIREMENTS; OPTIMAL COMBINATION; WAFER LEVEL PACKAGING;

ELECTRONICS PACKAGING;

EID: 4544344560     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2002.1185673     Document Type: Conference Paper

References (7)

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