A 2.29 Gbits/sec, 56 mW non-pipelined Rijndael AES encryption IC in a 1.8V, 0.18 μm CMOS technology

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2002, Pages 147-150

  Kuo, Henry ^a   Verbauwhede, Ingrid ^a   Schaumont, Patrick ^a  

^a University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; CRYPTOGRAPHY; ELECTRIC POWER UTILIZATION; FEEDBACK; SYSTEMS ANALYSIS; THROUGHPUT;

ADVANCED ENCRYPTION STANDARD (AES);

CMOS INTEGRATED CIRCUITS;

EID: 0036053417     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. The block cipher Rijndael
2. High performance single-chip FPGA Rijndael algorithm implementations
3. Hardware evaluation of the AES finalists
4. An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists