Speed-area trade-off for 10 to 100 Gbits/s throughput AES processor

Conference Record of the Asilomar Conference on Signals, Systems and Computers

Volumn 2, Issue , 2003, Pages 2147-2150

  Hodjat, Alireza ^a   Verbauwhede, Ingrid ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADVANCED ENCRYPTION STANDARD (AES); DATAPATHS; OPTICAL NETWORKS; PSEUDORANDOM NUMBERS;

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COST BENEFIT ANALYSIS; LOGIC DESIGN; OPTICAL SWITCHES; OPTIMIZATION; PROGRAM PROCESSORS; SCHEDULING; THROUGHPUT;

CRYPTOGRAPHY;

EID: 4143111537     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

1. National Institute of Standards and Technology (U.S.), Advanced Encryption Standard. Available at: http://csrc.nist.gov/Publication/drafts/ dfips-AES.pdf
2. M. Dworkin, SP 800-38A 2001, "Recommendation for Block Cipher Modes of Operations", December 01.
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4. http://www.nist.gov/aes/
5. H. Kuo, P. Schaumont, and I. Verbauwhede, "A 2,29 Gbits.sec, 56 mW non-pipelined Rijndael AES Encryption IC in a 1.8 V, 0.18 um CMOS technology," Proc. 2002 CICC, pp. 147-50, May 2002.
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9. T. Ichikawa et al, "Hardware Evaluation of the AES Finalists", in Proc. 3th AES Candidate Conference, New York, April 13-13, 2000.
10. I. Verbauwhede, P. Schaumont, H. Kuo, "design and Performance testing of a 2.29 Gb/s Rijndael Processor", IEEE Journal of Solid-State Cuitcuits (JSSC), March 2003.
11. K. Gaj and P. Chodowiec, "Fast Implementation and Fair Comparison of the Final Candidates for Advanced Encryption Standard Using Field Programmable Gate Arrays", CT-RSA 2001, LNCS 2020, pp. 84-99, 2001.