Robustness of sub-70nm dynamic circuits: Analytical techniques and scaling trends

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2001, Pages 23-24

  Anders, M ^a   Krishnamurthy, R ^a   Spotten, R ^a   Soumyanath, K ^a  

^a INTEL RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC RESPONSE; LOGIC GATES; MOS DEVICES; ROBUSTNESS (CONTROL SYSTEMS); SPURIOUS SIGNAL NOISE; TIME DOMAIN ANALYSIS;

DYNAMIC CIRCUITS;

LOGIC CIRCUITS;

EID: 0034784853     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)