A leakage tolerant high fan-in dynamic circuit design technique

European Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 309-312

  Kim, Jae Joon ^a   Roy, K ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS PROCESS TECHNOLOGY; DC NOISE; DOMINO CIRCUIT; DYNAMIC CIRCUITS; HIGH FAN-IN; LEAKAGE-TOLERANT; NOISE CHARACTERISTIC; NOISE IMMUNITY;

CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 84893702398     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. Berkeley Predictive Technology Model, http://wwwdecice. eecs.berkeley.edu/~ptm .
2. R. Krambeck, C. Lee and H. Law, "High-Speed Compact Circuits with CMOS", IEEE Journal of Solid State Circuits, vol. 17, No. 6, June 1982, pp.614-619.
3. V. De and S. Borkar, "Technology and design challenges for low power and high performance," Proc.of Intl. Symp. on Low Power Electronics and Design, pp.163-168, San Diego, CA, Aug. 1999.
4. R. Kumar, "Interconnect and Noise Immunity Design for the Pentium 4 Processor," Intel Technology Journal, Q1 2001 Issue, Feb. 2001.
5. M. Anders, R. Krishnamurthy, R. Spotten and K. Soumyanath, "Robustness of sub-70nm Dynamic Circuits: Analytical Techniques and Scaling Trends," to appear in 2001 Symposium on VLSI circuit, June 2001.
6. A. Chandrakasan, W. Bowhill and F. Fox, Design of High-Performance Microprocessor Circuits, pp221-225, IEEE Press, New York, 2001.
7. L. Wang, R. Krishnamurthy, K. Soumyanath and N. Shanbhag, "An Energy-Efficient Leakage-Tolerant Dynamic Circuit Techniques," Proc. of 2000 ASIC conference, pp221-225, 2000
8. A. Solomatnikov, D.Somasekhar, and K. Roy, "Skewed CMOS: Noise-Immune High-Performance Low Power Static Circuit Family," Proc. of European Solid-State Circuits Conference, 2000.