Materials and process integration issues in metal gate/high-k stacks and their dependence on device performance

ECS Transactions

Volumn 11, Issue 4, 2007, Pages 265-274

  Callegari, A ^a   Babich, K ^a   Zafar, S ^a   Ando, T ^a,b   Batson, P ^a   Narayanan, V ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b SONY CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON MOBILITY; LOGIC GATES; METALS; SILICA; SILICON; THRESHOLD VOLTAGE; WORK FUNCTION;

AFTER HIGH TEMPERATURE; DEVICE PERFORMANCE; HIGH ELECTRON MOBILITY; HIGH-PERFORMANCE CMOS; INTERFACIAL LAYER; MATERIALS AND PROCESS; METAL INTERACTIONS; SI/SIO2 INTERFACE;

DIELECTRIC MATERIALS;

EID: 45249123211     PISSN: 19385862     EISSN: 19386737     Source Type: Conference Proceeding    
DOI: 10.1149/1.2779566     Document Type: Conference Paper

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