Full-field wafer level thin film stress measurement by phase-stepping shadow Moiré

IEEE Transactions on Components and Packaging Technologies

Volumn 27, Issue 3, 2004, Pages 594-601

  Chen, Kuo Shen ^a   Chen, Terry Yuan Fang ^a   Chuang, Chia Cheng ^a   Lin, I Kuan ^a  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

MICROELECTROMECHANICAL DEVICES; MICROELECTRONICS; MOIRE FRINGES; PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION; SILICON NITRIDE; SILICON WAFERS; STRESS ANALYSIS; SURFACE TOPOGRAPHY;

PHASE STEPPING; SHADOW MOIRE; THIN FILM STRESS; WAFER CURVATURE;

THIN FILM DEVICES;

EID: 4444370127     PISSN: 15213331     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAPT.2004.831830     Document Type: Article

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