Warpage measurement of large area multitilted silicon substrates at various processing conditions

IEEE Transactions on Components and Packaging Technologies

Volumn 23, Issue 3, 2000, Pages 497-504

  Bhattacharya, Swapan K ^b   Ume, I Charles ^a,c   Dang, Anh X H ^c  

^a IEEE   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^c GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOROFLOAT ASSEMBLY; COEFFICIENT OF THERMAL EXPANSION (CTE); SHADOW MOIRES; WARPAGE MEASUREMENT;

ADHESIVES; CURING; MOIRE FRINGES; MULTICHIP MODULES; SEMICONDUCTING GLASS; SEMICONDUCTOR DEVICE MANUFACTURE; SILICON WAFERS; SUBSTRATES; THERMAL EXPANSION;

ELECTRONICS PACKAGING;

EID: 0034273596     PISSN: 15213331     EISSN: None     Source Type: Journal    
DOI: 10.1109/6144.868849     Document Type: Article

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