High level cache simulation for heterogeneous multiprocessors

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 287-292

  Pieper, Joshua J ^a   Mellan, Alain ^b   Paul, JoAnn M ^a   Thomas, Donald E ^a   Karim, Faraydon ^b  

^a CARNEGIE MELLON UNIVERSITY   (United States)

^b STMICROELECTRONICS   (Italy)

Author keywords

Design; Performance

Indexed keywords

ALGORITHMS; BENCHMARKING; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER SIMULATION; EMBEDDED SYSTEMS; ERROR ANALYSIS; MAPPING; MATHEMATICAL MODELS; SCHEDULING; SPEECH RECOGNITION;

HISTOGRAM; INSTRUCTION SET SIMULATORS (ISS); LOGARITHMIC BINNING; TRUNCATION ERRORS;

MICROPROCESSOR CHIPS;

EID: 4444230087     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/996566.996652     Document Type: Conference Paper

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