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Volumn 33, Issue 11, 1998, Pages 58-69

Data Speculation Support for a Chip Multiprocessor

Author keywords

[No Author keywords available]

Indexed keywords


EID: 0347600845     PISSN: 03621340     EISSN: None     Source Type: Journal    
DOI: 10.1145/291006.291020     Document Type: Article
Times cited : (27)

References (13)
  • 2
    • 0007997616 scopus 로고    scopus 로고
    • ARB: A hardware mechanism for dynamic reordering of memory references
    • May
    • M. Franklin and G. Sohi, "ARB: A hardware mechanism for dynamic reordering of memory references," IEEE Transactions on Computers, vol. 45, no. 5, pp. 552-571, May 1996.
    • (1996) IEEE Transactions on Computers , vol.45 , Issue.5 , pp. 552-571
    • Franklin, M.1    Sohi, G.2
  • 4
    • 0009376728 scopus 로고    scopus 로고
    • Considerations in the Design of Hydra: A Multiprocessor-on-a-Chip Microarchitecture
    • Stanford University, February
    • L. Hammond and K. Olukotun, Considerations in the Design of Hydra: a Multiprocessor-on-a-Chip Microarchitecture, Stanford University Technical Report No. CSL-TR-98-749, Stanford University, February 1998.
    • (1998) Stanford University Technical Report No. CSL-TR-98-749
    • Hammond, L.1    Olukotun, K.2
  • 5
    • 0025429331 scopus 로고
    • Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
    • Seattle, WA, June
    • N. P. Jouppi, "Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers," Proceedings of the 17th Annual International Symposium of Computer Architecture, pp. 364-373, Seattle, WA, June 1990.
    • (1990) Proceedings of the 17th Annual International Symposium of Computer Architecture , pp. 364-373
    • Jouppi, N.P.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.