A digitally controlled PLL for digital SOCs

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2003, Pages

  Olsson, Thomas ^a   Nilsson, Peter ^a  

^a LUND UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POTENTIAL; ERROR ANALYSIS;

DIGITAL SYSTEMS;

PHASE LOCKED LOOPS;

EID: 0038420044     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. P. Nilsson and M. Torkelson, "A Monolitic Digital Clock-Generator for On-Chip Clocking of Custom DSP's", IEEE J. Solid-State Circuits, vol.31, No. 5, pp. 700-706, May. 1996.
2. T. Olsson, P. Nilsson, T. Meincke, A. Hemani and M. Torkelson. "A Digitally Controlled Low-Power Clock Multiplier for Globally Asynchronous Locally Synchronous Designs", In Proceedings of ISCAS'2000, Geneva, May 2000.
3. R. E. Best, Phase-locked loops, McGraw-Hill, 1984.