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Volumn , Issue , 2003, Pages 54-59

VLSI interconnect modeling at multi-GHz frequencies incorporating inductance

Author keywords

Clocks; Data mining; Delay; Frequency; Impedance; Inductance; Integrated circuit interconnections; Springs; Very large scale integration; Wire

Indexed keywords

CLOCKS; DATA MINING; ELECTRIC IMPEDANCE; INDUCTANCE; MIXED SIGNAL INTEGRATED CIRCUITS; SPRINGS (COMPONENTS); VLSI CIRCUITS; WIRE;

EID: 4344673443     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SSMSD.2003.1190396     Document Type: Conference Paper
Times cited : (3)

References (14)
  • 1
    • 33747530935 scopus 로고    scopus 로고
    • Clock Distribution Networks in Synchronous Digital Integrated Circuits
    • Invited paper, May
    • E. Friedman, "Clock Distribution Networks in Synchronous Digital Integrated Circuits", Invited paper, Proc. of the IEEE, No.5, May 2001.pp.3-14.
    • (2001) Proc. of the IEEE , Issue.5 , pp. 3-14
    • Friedman, E.1
  • 2
    • 84884683214 scopus 로고    scopus 로고
    • Clock Design of 300MHz 128-bit 2-way Superscalar μ-processor
    • F. Ishihara, C. Klingner, K. Agawa"Clock Design of 300MHz 128-bit 2-way Superscalar μ-processor", Proc. of DAC00,2000,p.647-52.
    • Proc. of DAC00,2000 , pp. 647-652
    • Ishihara, F.1    Klingner, C.2    Agawa, K.3
  • 5
    • 84888035000 scopus 로고    scopus 로고
    • A clock Tree Topology Extraction Algorithm For Improving The Tolerance of Clock Distribution Networks to Delay Uncertainly
    • D. Velenis, E. Friedman, M. Ppaefthymiou,"A clock Tree Topology Extraction Algorithm For Improving The Tolerance of Clock Distribution Networks to Delay Uncertainly", ISCAS 2001,pp.422-425.
    • ISCAS 2001 , pp. 422-425
    • Velenis, D.1    Friedman, E.2    Ppaefthymiou, M.3
  • 7
    • 84962873853 scopus 로고    scopus 로고
    • Analysis of Interconnect Delay for 0.18um Technology and Beyond
    • S. Wu, B. Liew.K. Young, C. Yu, S. Sun, "Analysis of Interconnect Delay for 0.18um Technology and Beyond",IITC-99,pp.68-69.
    • IITC-99 , pp. 68-69
    • Wu, S.1    Liew, B.2    Young, K.3    Yu, C.4    Sun, S.5
  • 8
    • 0031641251 scopus 로고    scopus 로고
    • Interconnect Inductance Effects on Delay and Cross Talks for Long on-Chip Nets With Fast Input Slew Rates
    • M. Anthony, M. Darley,"Interconnect Inductance Effects on Delay and Cross Talks for Long on-Chip Nets With Fast Input Slew Rates", ISCAS'98,1998,pp. 248-251.
    • (1998) ISCAS'98 , pp. 248-251
    • Anthony, M.1    Darley, M.2
  • 10
    • 0001032562 scopus 로고
    • Induct. Cal. In a Complex IC Env
    • July
    • A.E. Ruheli,"Induct. Cal. In a Complex IC Env", IBM J. of Res., July 1972, pp. 470-480.
    • (1972) IBM J. of Res. , pp. 470-480
    • Ruheli, A.E.1
  • 11
    • 0034841994 scopus 로고    scopus 로고
    • Modeling and Analysis of Differential Signaling for Minimizing Inductance Cross-Talk
    • Y. Massoud, J. Kawa, D. MacMillen, J. White"Modeling and Analysis of Differential Signaling for Minimizing Inductance Cross-Talk", DAC 2001,pp.804-809.
    • DAC 2001 , pp. 804-809
    • Massoud, Y.1    Kawa, J.2    MacMillen, D.3    White, J.4
  • 13
    • 0034853859 scopus 로고    scopus 로고
    • Min/Max On-Chip Inductance Models and Delay Metrics
    • Y. Lu, M. Celik, T. Young, L. Pileggi,"Min/Max On-Chip Inductance Models and Delay Metrics", DAC 2001, p.341-346,2001.
    • (2001) DAC 2001 , pp. 341-346
    • Lu, Y.1    Celik, M.2    Young, T.3    Pileggi, L.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.