Clock tree synthesis for high performance ASICs

Fourth Annual IEEE International ASIC Conference and Exhibit

Volumn , Issue , 1991, Pages

  Burkis, Joe ^a  

^a MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS; ELECTRIC LOSSES; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUITS; TIMING CIRCUITS; TREES (MATHEMATICS); WAVEFORM ANALYSIS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CLOCK TREE SYNTHESIS; HIGH PERFORMANCE CLOCKING NETWORK; MAXIMUM CLOCK SKEW; SKEW AND INSERTION DELAY;

BUFFER CIRCUITS;

EID: 0026289125     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)