Using all signed-digit representations to design single integer multipliers using subexpression elimination

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 3, Issue , 2004, Pages

  Dempster, A G ^a   Macleod, M D ^b  

^a UNIVERSITY OF WESTMINSTER   (United Kingdom)

^b QINETIQ   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CANONIC SIGNED DIGIT CODE (CSD); GRAPHICAL MULTIPLIER DESIGN; INTEGER MULTIPLIERS; MINIMAL SIGNED DIGIT (MSD);

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER SOFTWARE; FIR FILTERS; OPTIMIZATION; TOPOLOGY; VLSI CIRCUITS;

INTEGER PROGRAMMING;

EID: 4344645621     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)

1. Algirdas Avizienis, "Signed-digit representation for fast parallel arithmetic", IRE Trans Electronic Computers, vol 10, pp389-400, Sep 1961
2. Harvey L Garner, "Number Systems and Arithmetic", Advances in Computers, vol 6, pp131-194, 1965
3. George W Reitweisner, "Binary Arithmetic", Advances in Computers, vol 1, pp 232-308, 1960
4. Kai Hwang, "Computer Arithmetic: Principles, Architecture and Design", Wiley, 1979
5. D R Bull and D H Horrocks, "Primitive operator digital filters", IEE Proc. G, vol 138, no 3, pp401-412, 1991
6. A G Dempster and M D Macleod, "Constant integer multiplication using minimum adders", IEE Proc CDS, vol 141, no 5, pp407-413, Oct 1994
7. Robert Bernstein, "Multiplication by Integer Constants", Software-Practice and Experience, vol 16, no 7, pp641-652, Jul 1986
8. A G Dempster and M D Macleod, "General algorithms for reduced-adder integer multiplier design", Elec Let, vol 31, no 21, pp 1800-1802, Oct 1995
9. Oscar Gustafsson, Andrew G Dempster and Lars Wanhammer, "Extended Results for Minimum-Adder Constant Integer Multipliers", Proc ISCAS 2002, Phoenix, May 27-29 2002, ppI73-76
10. Dongning Li, "Minimum number of adders for implementing a multiplier and its application to the design of multiplierless digital filters", IEEE Trans C&S II, vol 42, no 7, pp 453-460, July 1995
11. A G Dempster and M D Macleod, "Comments on 'Minimum number of adders for implementing a multiplier and its application to the design of multiplierless digital filters'", IEEE Trans C&S II, vol. 45, no. 2, pp. 242-243, Feb 1998
12. Richard Hartley, "Optimization of canonic signed digit multipliers for filter design", In ISCAS91, pp 1992-1995, 1991
13. R I Hartley, "Subexpression Sharing in Filters Using Canonic Signed-Digit Multipliers", IEEE Trans Circuits And Systems II, vol.43, no.10, pp.677-688, 1996
14. M Potkonjak, M B Srivastava and A Chandrakasan, "Multiple constant multiplications: efficient and versatile framework and algorithms for exploring common subexpression elimination", IEEE Trans Computer-Aided Design of IC Systems, vol. 15, no. 2. pp151-165, 1996
15. R Pasko et al, "A new algorithm for elimination of common subexpressions", IEEE Trans Computer-Aided Design of IC Systems, vol. 18, no. 1, pp58-68, 1999
16. In-Cheol Park and Hyeong-Ju Kang, "Digital filter synthesis based on an algorithm to generate all minimal signed digit representations", IEEE Trans Computer-Aided Design of IC Systems, vol. 12, no. 12. pp1525-1529, 2002
17. A G Dempster and M D Macleod, "Generation of Signed-Digit Representations for Integer Multiplication", submitted to Electronics Letters
18. A G Dempster and M D Macleod, "Design of Integer Multipliers using Subexpression Elimination Applied to all Possible Signed-Digit Representations", submitted to IEEE Trans Computer-Aided Design of IC Systems