Comments on "minimum number of adders for implementing a multiplier and its application to the design of multiplierless digital filters"

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 45, Issue 1, 1998, Pages 242-243

  Dempster, A G ^a   Macleod, M D ^a  

^a UNIVERSITY OF WESTMINSTER   (United Kingdom)

Author keywords

Digital filters; Multiplication, shift and add multiplication

Indexed keywords

EID: 0009527461     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.661661     Document Type: Article

References (8)

1. A. G. Dempster and M. D. Macleod Multiplication by an integer using minimum adders," in IEE Colloquium Math. Aspects Signal Processing, Dig. No. 1994/034, Feb. 1994, pp. 11/1-11/4.
2. Constant integer multiplication using minimum adders," Proc. Inst. Elect. Eng., vol. 141, pp. 40713, Oct. 1994.
3. R. Bernstein Multiplication by integer constants," Softw.-Pract. Exp., vol. 16, pp. 641-652, July 1986.
4. A. G. Dempster and M. D. Macleod General algorithms for reducedadder integer multiplier design," Electron. Lett., vol. 31, pp. 1800-1802, Oct. 1995.
5. D. R. Bull and D. H. Horrocks Primitive operator digital filters," Proc. Inst. Elect. Eng., vol. 138, pt. G, pp. 40112, June 1991.
6. A. G. Dempster and M. D. Macleod Use of minimum-adder multiplier blocks in FIR digital filters," IEEE Trans. Circuits Syst. II, vol. 42, pp. 569-577, Sept. 1995.
7. Use of multiplier blocks to reduce filter complexity," in Proc. ISCAS'94, London, May-June 1994, vol. 4, pp. 263-266.
8. A. G. Dempster Digital filter design for low-complexity implementation," Ph.D. dissertation, Univ. Cambridge, England, June 1995.