Extended results for minimum-adder constant integer multipliers

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 2002, Pages 73-76

  Gustafsson, Oscar ^a   Dempster, Andrew G ^b   Wanhammar, Lars ^a  

^a LINKÖPING UNIVERSITY   (Sweden)

^b UNIVERSITY OF WESTMINSTER   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ALGORITHMS; DIGITAL SIGNAL PROCESSING; ELECTRIC NETWORK TOPOLOGY; GRAPH THEORY; LOGIC GATES; SET THEORY; THEOREM PROVING;

CANONIC SIGNED DIGIT; DIRECTED ACYCLIC GRAPHS; GRAPH COEFFICIENT SET;

MULTIPLYING CIRCUITS;

EID: 0036283460     PISSN: 02714310     EISSN: None     Source Type: Journal    
DOI: 10.1109/ISCAS.2002.1009780     Document Type: Article

References (10)

1. Signed-digit number representation for fast parallel arithmetic
2. Multiplication by integer constants
3. Constant integer multiplication using minimum adders
4. Minimum number of adders for implementing a multiplier and its application to the design of multiplierless digital filters
5. General algorithms for reduced-adder integer multiplier design
6. Comments on 'minimum number of adders for implementing a multiplier and its application to the design of multiplierless digital filters
7. Primitive operator digital filters
8. Minimum-adder integer multipliers using carry-save adders
9. Use of minimum-adder multiplier blocks in FIR digital filters