A heuristic approach to synthesize Boolean functions using TANT network

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 2004, Pages

  Babu, Hafiz Md Hasan ^a   Islam, Md Rafiqul ^a   Nazmul, Rumana ^a   Haque, Md Anwarul ^a   Chowdhury, Ahsan Raja ^a  

^a UNIVERSITY OF DHAKA   (Bangladesh)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; C (PROGRAMMING LANGUAGE); CAMERAS; DATA STRUCTURES; DIGITAL DEVICES; HEURISTIC METHODS; PROBLEM SOLVING;

BINARY LOGIC FUNCTIONS; DIGITAL CAMERAS; HEURISTIC ALGORITHMS; POWER CONSUMPTION;

BOOLEAN FUNCTIONS;

EID: 4344568754     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. E.J. McClusky, "Minimization of Boolean functions", Bell System Technical Journal, Vol. 35, no.5, pp.1417-1444, November 1956.
2. P. Tison, "Generalization if consensus theory and application in minimization of Boolean function", IEEE Trans. Electronic Computers, vol. EC-16, pp, 446-456, August 1967.
3. Kyung Shik Koh, "A minimization technique for TANT network", IEEE transactions on computer, pp 105-107, January 1971.
4. T. Tanaka, T. Tanzawa and K. Takeuchi, "A 3.4-Mbyte/sec Programming 3-Level NAND Flash Memory Saving 40% Die Size Per Bit", Symposium on VLSI Circuits, keyato, Japan, 12-14 June, 1997.
5. H.M.H. Babu, M.R. Islam, S.M.A. Chowdhury, A.R Chowdhury, "An Improved Method for Minimization of Circuit Using TANT Network", accepted for publication in science journal, University of Dhaka.
6. M.A. Marin, "Synthesis of TANT Networks using Boolean Analyser", The Comp Journal, Vol. 12 No. 3 August 1969.
7. M.A. Perkowski, M.C. Jeske, "Multiple-Valued Input TANT network", ISMVL 1994, pp 334-341.
8. H.M.H.Babu, M.R. Islam, S.M.A.Chowdhury, A.R Chowdhury, "Synthesis of Full Adder Circuit Using Reversible Logic" Proceedings on 17th Int'l Conf. on VLSI Design 2004, January 5-9, 2004, Mumbai, India
9. H.M.H. Babu, M.R. Islam, S.M.A. Chowdhury, A.R Chowdhury" Reversible Logic Synthesis for Minimization of Full-Adder Circuit" Proceedings on DSD 2003, pp (50-54), Antalya, Turkey.