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Volumn 21, Issue 4, 2004, Pages 314-321

On-chip digital jitter measurement, from megahertz to gigahertz

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; BUILT-IN SELF TEST; JITTER; OSCILLOGRAPHS; PROBABILITY DENSITY FUNCTION; PROBABILITY DISTRIBUTIONS; WAVEFORM ANALYSIS;

EID: 4344566297     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2004.38     Document Type: Article
Times cited : (73)

References (9)
  • 1
    • 0034994760 scopus 로고    scopus 로고
    • A method for measuring the cycle-to-cycle period jitter of high-frequency clock signals
    • IEEE CS Press
    • T. Yamaguchi et al., "A Method for Measuring the Cycle-to-Cycle Period Jitter of High-Frequency Clock Signals," Proc. VLSI Test Symp. (VTS 01), IEEE CS Press, 2001, pp. 102-110.
    • (2001) Proc. VLSI Test Symp. (VTS 01) , pp. 102-110
    • Yamaguchi, T.1
  • 2
    • 0033315398 scopus 로고    scopus 로고
    • BIST for phase-locked loops in digital applications
    • IEEE Press
    • S. Sunter and A. Roy, "BIST for Phase-Locked Loops in Digital Applications," Proc. Int'l Test Conf. (ITC 99), IEEE Press, 1999, pp. 532-540.
    • (1999) Proc. Int'l Test Conf. (ITC 99) , pp. 532-540
    • Sunter, S.1    Roy, A.2
  • 3
    • 17144435893 scopus 로고    scopus 로고
    • A high resolution CMOS time-to-digital converter utilizing a vernier delay line
    • Feb
    • P. Dudek, S. Szczepanski, and J. Hatfield, "A High Resolution CMOS Time-to-Digital Converter Utilizing a Vernier Delay Line," IEEE J. Solid-State Circuits, vol. 35, no. 2, Feb. 2000, pp. 240-247.
    • (2000) IEEE J. Solid-State Circuits , vol.35 , Issue.2 , pp. 240-247
    • Dudek, P.1    Szczepanski, S.2    Hatfield, J.3
  • 5
    • 0035684160 scopus 로고    scopus 로고
    • A synthesizable, fast and high-resolution timing measurement device using a component-invariant vernier delay line
    • IEEE Press
    • A. Chan and G. Roberts, "A Synthesizable, Fast and High-Resolution Timing Measurement Device Using a Component-Invariant Vernier Delay Line," Proc. Int'l Test Conf. (ITC 01), IEEE Press, 2001, pp. 858-867.
    • (2001) Proc. Int'l Test Conf. (ITC 01) , pp. 858-867
    • Chan, A.1    Roberts, G.2
  • 6
    • 0036575437 scopus 로고    scopus 로고
    • Embedded timing analysis: A SoC infrastructure
    • May-June
    • S. Tabatabaei and A. Ivanov, "Embedded Timing Analysis: A SoC Infrastructure," IEEE Design & Test of Computers, vol. 19, no. 3, May-June 2002, pp. 22-34.
    • (2002) IEEE Design and Test of Computers , vol.19 , Issue.3 , pp. 22-34
    • Tabatabaei, S.1    Ivanov, A.2
  • 7
    • 0035005145 scopus 로고    scopus 로고
    • An on-chip short-time interval measurement technique for testing high-speed communication links
    • IEEE CS Press
    • J.-L. Huang and K.-T. Cheng, "An On-Chip Short-Time Interval Measurement Technique for Testing High-Speed Communication Links," Proc. VLSI Test Symp. (VTS 01), IEEE CS Press, 2001, pp. 380-385.
    • (2001) Proc. VLSI Test Symp. (VTS 01) , pp. 380-385
    • Huang, J.-L.1    Cheng, K.-T.2
  • 8
    • 0036446488 scopus 로고    scopus 로고
    • Architecting millisecond test solutions for wireless phone RFIC's
    • IEEE Press
    • J. Ferrario, R. Wolf, and S. Moss, "Architecting Millisecond Test Solutions for Wireless Phone RFIC's," Proc. Int'l Test Conf. (ITC 02), IEEE Press, 2002, pp. 1151-1158.
    • (2002) Proc. Int'l Test Conf. (ITC 02) , pp. 1151-1158
    • Ferrario, J.1    Wolf, R.2    Moss, S.3
  • 9
    • 0348233232 scopus 로고    scopus 로고
    • An 8-Gb/s simultaneous bidirectional link with on-die waveform capturec
    • Dec
    • B. Casper et al., "An 8-Gb/s Simultaneous Bidirectional Link with On-Die Waveform Capture," IEEE J. Solid-State Circuits, vol. 38, no. 12, Dec. 2003, pp. 2111-2120.
    • (2003) IEEE J. Solid-State Circuits , vol.38 , Issue.12 , pp. 2111-2120
    • Casper, B.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.