A method for measuring the cycle-to-cycle period jitter of high-frequency clock signals

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2001, Pages 102-110

  Yamaguchi, T J ^a   Soma, M ^a   Halter, D ^a   Raina, R ^a   Nissen, J ^a   Ishida, M ^a  

^a ADVANTEST CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BANDPASS FILTERS; CATHODE RAY OSCILLOSCOPES; CORRELATION METHODS; DIFFERENTIAL EQUATIONS; ERROR ANALYSIS; JITTER; MICROPROCESSOR CHIPS; PROBABILITY DISTRIBUTIONS;

CYCLE TO CYCLE PERIOD JITTER; HIGH FREQUENCY CLOCK SIGNALS; PHASE QUANTIZATION ERRORS;

PHASE LOCKED LOOPS;

EID: 0034994760     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

1. A 1 GHz single-issue 64b powerPC processor
2. Analyze jitter to improve high-speed design
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5. Comments on the interpretation of instantaneous frequency
6. Jitter analysis <101>: A primer for jitter testing of PLL circuits