A synthesizable, fast and high-resolution timing measurement device using a component-invariant vernier delay line

IEEE International Test Conference (TC)

Volumn , Issue , 2001, Pages 858-867

  Chan, Antonio H ^a   Roberts, Gordon W ^a  

^a MCGILL UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS; INTEGRATED CIRCUIT LAYOUT; PHASE LOCKED LOOPS; SHIFT REGISTERS; TIME MEASUREMENT; TIMING JITTER;

DELAY LOCK LOOPS (DLL); TIMING MEASUREMENT DEVICES;

TIMING CIRCUITS;

EID: 0035684160     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

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3. Time memory cell VLSI for the PHENIX drift chamber
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5. BIST for phase-locked loops in digital applications
6. Circuits for on-chip sub-nanosecond signal capture and characterization
7. A high-resolution CMOS time-to-digital converter utilizing a vernier delay line
8. Testing and characterizing jitter in 100BASE-TX and 155.52 Mbit/s ATM devices with a 1 Gsamples/s AWG in an ATE system
9. Analysis of metastability operations in D-latches
10. Experimental studies of metastability behavior of sub-micron CMOS ASIC flip flops
11. Characterizing metastability