An on-chip short-time interval measurement technique for testing high-speed communication links

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2001, Pages 380-385

  Huang, J L ^a   Cheng, K T ^a  

^a University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG STORAGE; ANALOG TO DIGITAL CONVERSION; COMPUTER HARDWARE; COMPUTER SIMULATION; MICROPROCESSOR CHIPS; PHASE LOCKED LOOPS; SAMPLING; TELECOMMUNICATION LINKS; TIME DOMAIN ANALYSIS; TRANSCEIVERS;

HIGH SPEED COMMUNICATION LINKS; ON-CHIP SHORT-TIME INTERVAL MEASUREMENT; POST-MEASUREMENT ANALYSIS;

BUILT-IN SELF TEST;

EID: 0035005145     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. High speed digital transceivers: A challenge for manufacturing
2. Testing methodology for FireWire
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6. A low-power CMOS time-to-digital converter
7. A time digitizer CMOS gate-array with a 250 ps time resolution
8. Time interval measurement using time-to-voltage conversion with built-in dual-slope A/D conversion