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Volumn 1, Issue , 2004, Pages

Floating gate comparator with automatic offset manipulation functionality

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); ANALOG TO DIGITAL CONVERSION; AUTOMATION; COMPUTER PROGRAMMING; DELAY CIRCUITS; DESIGN FOR TESTABILITY; DIGITAL ARITHMETIC; ELECTRIC POTENTIAL; FEEDBACK; GATES (TRANSISTOR); SIGNAL PROCESSING;

EID: 4344560543     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (9)

References (11)
  • 1
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    • Design techniques for high-speed, high-resolution comparators
    • December
    • B. Razavi and B.A. Wooley, "Design techniques for high-speed, high-resolution comparators," IEEE JSSC, vol. 27, no. 12, pp. 1916-1926, December 1992.
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    • Razavi, B.1    Wooley, B.A.2
  • 2
    • 0035043140 scopus 로고    scopus 로고
    • Floating-gate adaptation for focal-plane online nonuniformity correction
    • January
    • M. Cohen and G. Cauwenberghs, "Floating-gate adaptation for focal-plane online nonuniformity correction," IEEE TCASII, vol. 48, no. 1, pp. 83-89, January 2001.
    • (2001) IEEE TCASII , vol.48 , Issue.1 , pp. 83-89
    • Cohen, M.1    Cauwenberghs, G.2
  • 3
    • 0036290585 scopus 로고    scopus 로고
    • A temperature independent trimmable current source
    • May
    • S. Shah and S. Collins, "A temperature independent trimmable current source," in IEEE Proc. ISCAS, May 2002, vol. 1, pp. 1713-1716.
    • (2002) IEEE Proc. ISCAS , vol.1 , pp. 1713-1716
    • Shah, S.1    Collins, S.2
  • 4
    • 0035051604 scopus 로고    scopus 로고
    • A programmable current mirror for analog trimming using single poly floating-gate devices in standard CMOS technology
    • January
    • S.A. Jackson, J.C. Killens, and B.J. Blalock, "A programmable current mirror for analog trimming using single poly floating-gate devices in standard CMOS technology," IEEE TCASII, vol. 48, no. 1, pp. 100-102, January 2001.
    • (2001) IEEE TCASII , vol.48 , Issue.1 , pp. 100-102
    • Jackson, S.A.1    Killens, J.C.2    Blalock, B.J.3
  • 5
    • 0038529372 scopus 로고    scopus 로고
    • A 300-MS/s 14-bit digital-to-analog converter in logic CMOS
    • May
    • John Hyde, Todd Humes, Chris Diorio, Mike Thomas, and Miquel Figueroa, "A 300-MS/s 14-bit digital-to-analog converter in logic CMOS," IEEE JSSC, vol. 38, no. 5, pp. 734-740, May 2003.
    • (2003) IEEE JSSC , vol.38 , Issue.5 , pp. 734-740
    • Hyde, J.1    Humes, T.2    Diorio, C.3    Thomas, M.4    Figueroa, M.5
  • 6
    • 0035052016 scopus 로고    scopus 로고
    • An autozeroing floating-gate amplifier
    • January
    • P. Hasler, B.A. Minch, and C. Diorio, "An autozeroing floating-gate amplifier," IEEE TCASII, vol. 48, no. 1, pp. 74-82, January 2001.
    • (2001) IEEE TCASII , vol.48 , Issue.1 , pp. 74-82
    • Hasler, P.1    Minch, B.A.2    Diorio, C.3
  • 7
    • 0038496831 scopus 로고    scopus 로고
    • An auto-input-offset removing floating gate pseudo-differential transconductor
    • May
    • T.G. Constandinou, J. Georgiou, and C. Toumazou,' "An auto-input-offset removing floating gate pseudo-differential transconductor," in IEEE Proc. ISCAS, May 2003, vol. 1, pp. 169-172.
    • (2003) IEEE Proc. ISCAS , vol.1 , pp. 169-172
    • Constandinou, T.G.1    Georgiou, J.2    Toumazou, C.3
  • 8
    • 0035046840 scopus 로고    scopus 로고
    • Correlation learning rule in floating-gate pFET synapses
    • January
    • P. Hasler and J. Dugger, "Correlation learning rule in floating-gate pFET synapses," IEEE TCASII, vol. 48, no. 1, pp. 65-73, January 2001.
    • (2001) IEEE TCASII , vol.48 , Issue.1 , pp. 65-73
    • Hasler, P.1    Dugger, J.2
  • 9
    • 0035051734 scopus 로고    scopus 로고
    • Continuous-time feedback in floating-gate MOS circuits
    • January
    • P. Hasler, "Continuous-time feedback in floating-gate MOS circuits," IEEE TCASII, vol. 48, no. 1, pp. 56-64, January 2001.
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    • Hasler, P.1
  • 10
    • 0036294819 scopus 로고    scopus 로고
    • A simulation model for floating-gate MOS synapse transistors
    • May
    • K. Rahimi, C. Diorio, C. Hernandez, and M.D. Brockhausen, "A simulation model for floating-gate MOS synapse transistors," in IEEE Proc. ISCAS, May 2002, vol. 2, pp. 532-535.
    • (2002) IEEE Proc. ISCAS , vol.2 , pp. 532-535
    • Rahimi, K.1    Diorio, C.2    Hernandez, C.3    Brockhausen, M.D.4
  • 11
    • 0035696160 scopus 로고    scopus 로고
    • A 6-b 1.3-gsample/s a/d converter in 0.35-μm CMOS
    • December
    • M. Choi and A.A. Abidi, "A 6-b 1.3-gsample/s a/d converter in 0.35-μm CMOS," IEEE JSSC, vol. 36, no. 12, pp. 1847-1858, December 2001.
    • (2001) IEEE JSSC , vol.36 , Issue.12 , pp. 1847-1858
    • Choi, M.1    Abidi, A.A.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.