A programmable current mirror for analog trimming using single-poly floating-gate devices in standard CMOS technology

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 48, Issue 1, 2001, Pages 100-102

  Jackson, Scott A ^a   Killens, Jacob C ^a   Blalock, Benjamin J ^a  

^a MISSISSIPPI STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; THRESHOLD VOLTAGE;

ANALOG TRIMMING; FLOATING-GATE DEVICES; PROGRAMMABLE CURRENT MIRROR;

GATES (TRANSISTOR);

EID: 0035051604     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.913192     Document Type: Article

References (9)

1. Optimizing MOS transistor mismatch
2. Matching properties of MOS transistors for precision analog design
3. Characterization and modeling of mismatch in MOS transistors for precision analog design
4. Design and implementation of an untrimmed MOSFET-only 10-bit A/D converter with -79-dB THD
5. An analog trimming circuit based on a floating-gate device
6. Trimming analog circuits using floating-gate analog MOS memory
7. EEPROM as an analog storage device, with particular applications in neural networks
8. Automatic and continuous offset compensation of MOS operational amplifiers using floating-gate transistors
9. A single poly EEPROM cell structure for use in standard CMOS processes