OpenFPGA CoreLib core library interoperability effort

Parallel Computing

Volumn 34, Issue 4-5, 2008, Pages 231-244

  Wirthlin, M ^a   Poznanovic, D ^b   Sundararajan, P ^c   Coppola, A ^d   Pellerin, D ^e   Najjar, W ^f   Bruce, R ^g,h   Babst, M ⁱ   Pritchard, O ^j   Palazzari, P ^k   Kuzmanov, G ^l  

^a BRIGHAM YOUNG UNIVERSITY   (United States)

^b SRC Computers Inc   (United States)

^c XILINX INC   (United States)

^d OptNgn Software LL   (United States)

^e Impulse Accelerated Technologies   (United States)

^f University of California Riverside   (United States)

^g Boolean House   (United Kingdom)

^h INSTITUTE FOR SYSTEM LEVEL INTEGRATION   (United Kingdom)

ⁱ DSPlogic Inc   (United States)

^j ALTERA CORPORATION   (United States)

^k ENEA C R CASACCIA   (Italy)

^l DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

more..

Author keywords

Core library; HDL cores; Reconfigurable computing; Standards

Indexed keywords

COMPUTER AIDED SOFTWARE ENGINEERING; HIGH LEVEL LANGUAGES; INTEROPERABILITY; NETWORK ARCHITECTURE; STANDARDIZATION;

CORE LIBRARY; FPGA DESIGN TOOLS; HIGH-LEVEL LANGUAGE COMPILERS; RECONFIGURABLE COMPUTING;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 43149108823     PISSN: 01678191     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.parco.2008.03.004     Document Type: Article

References (28)

1. OpenFPGA Consortium, www.openfpga.org.
2. OPENCores Consortium, www.opencores.org.
3. Open Core Protocol International Partnership (OCP-OP), www.ocpip.org.
4. SPIRIT Consortium, www.spiritconsortium.org.
5. VSI Alliance, www.vsi.org.
6. Silicon Integration Initiative (Si2), www.Si2.org.
7. Riverside Optimizing Compiler for Reconfigurable Computing (ROCCC), .
8. Z. Guo, A.B. Buyukkurt, W. Najjar, Input data reuse in compiling window operations onto reconfigurable hardware, in: Proceedings of the ACM Symposium on Languages, Compilers and Tools for Embedded Systems (LCTES 2004), Washington, DC, June 2004.
9. Z. Guo, A. Mitra, W. Najjar, Automation of IP core interface generation for reconfigurable computing, in: 16th International Conference on Field Programmable Logic and Applications (FPL 2006), Madrid, Spain, August 2006.
10. Impulse Accelerated Technologies, www.ImpulseC.com.
11. Nallatech, www.nallatech.com.
12. Justin L. Tripp, Kristopher D. Peterson, Christine Ahrens, Jeffrey D. Poznanovic, Maya Gokhale: Trident: an FPGA compiler framework for floating-point algorithms, in: Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL 2005), pp. 317-322.
13. SRC Computers Inc., www.srccomp.com.
14. DSPLogic, www.dsplogic.com.
15. C-to-Hardware Acceleration (C2H), www.altera.com/products/ip/processors/nios2/tools/c2h/ni2-c2h.html.
16. Ylichron Harwest Complier, .
17. Vassiliadis S., Wong S., Gaydadjiev G., Bertels K., Kuzmanov G., and Moscu Panainte E. The MOLEN polymorphic processor. IEEE Transactions on Computers 53 11 (2004) 1363-1375
18. Y. Yankova, G. Kuzmanov, K. Bertels, G. Gaydadjiev, Yi Lu, S. Vassiliadis, DWARV: DelftWorkbench Automated Reconfigurable VHDL Generator, in: Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL'07), Amsterdam, The Netherlands, August 2007, pp. 697-701.
19. The MOLEN Prototype .
20. IP-XACT User Guide v1.2 for RTL, SPIRIT Consortium, July 2006.
21. VHDL 2006 Packages, .
22. OpenFPGA CoreLib, .
23. Dave Bennett, Prasanna Sundararajan, Jeff Mason, Eric Dellinger, An FPGA-oriented target language for HLL compilation, The Reconfigurable Systems Summer Institute, 2006.
24. Y. Li, W. Chu, Implementations of single precision floating point square root on fpgas, in: Proceedings, the 5th Annual IEEE Symposium on FPGA Custom Computing Machines, 1997, pp. 226-232.
25. E. Roesler, B.E. Nelson, Novel optimizations for floating-point units in a modern FPGA architecture, in: Proceedings of the 12th International Conference on Field-Programmable Logic, 2002, pp. 637-646.
26. X. Wang, B.E. Nelson, Tradeoffs of designing floating-point division and square root on virtex FPGAs, in: Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), April 2003, pp. 195-203.
27. X. Wang, S. Braganza, M. Leeser, Advanced components in the variable precision floating-point library, in: IEEE Symposium on Field-programmable Custom Computing Machines (FCCM'06), April 2006, pp. 249-258.
28. R. Andraka, A Survey of CORDIC Algorithms for FPGAs, in: Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays (FPGA'98), Monterey, CA, Feb. 22-24, 1998, pp. 191-200.