Automation of IP core interface generation for reconfigurable computing

Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL

Volumn , Issue , 2006, Pages 475-480

  Guo, Zhi ^a   Mitra, Abhishek ^b   Najjar, Walid ^b  

^a Department of Electrical Engineering ^*

^b University of California Riverside   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

C FUNCTIONS; FIELD PROGRAMMABLE LOGIC (FPL); INTERFACE GENERATION; INTERNATIONAL CONFERENCES; IP CORES; RE CONFIGURABLE COMPUTING (RCC); RECONFIGURABLE PLAT FORMS; RUN TIME RECONFIGURATION (RTR); SOURCE CODING;

DESCRIBING FUNCTIONS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FUZZY LOGIC;

INTERNET PROTOCOLS;

EID: 46249087626     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2006.311254     Document Type: Conference Paper

References (11)

1. SUIF Compiler System, http://suif.stanford.edu, 2006
2. Machine-SUIF. 2006 http://www.eecs.harvard.edu/hube/research/machsuif. html
3. G. Holloway. The Machine-SUIF Static Single Assignment Library. Division of Engineering and Applied Sciences, Harvard University 2002.
4. Z. Guo, B. Buyukkurt, W. Najjar and K. Vissers. Optimized Generation of Data-path from C Codes for FPGAs, Int. ACM/IEEE Design, Automation and Test in Europe Conference (DATE 2005). Munich, Germany, March, 2005.
5. Virtual Socket Interface Association (VSIA), http://www.vsi.org/, 2006
6. P.Chou, G. Ortega, G. Borriello. Interface co-synthesis techniques for embedded systems, Int. Conf. on Computer Aided Design, San Jose, USA, 1995.
7. R. Lysecky and F. Vahid. Prefetching for Improved Bus Wrapper Performance in Cores, ACM Transactions on Design Automation of Electronic Systems, Vol. 7, No. 1, pp. 58-90, January 2002.
8. J. Zhu. MetaRTL: Raising the abstraction level of RTL design, Design, Automation, and Test in Europe, Munich, Germany, 2001
9. V. Stuikys, R. Damasevicius. Soft IP Customisation Model Based on Metaprogramming Techniques, Informatica, Lith. Acad. Sci. 15(1): 111-126 (2004)
10. J. Tripp, K. Peterson, C. Ahrens, J. Poznanovic, M. Gokhale. Trident: An FPGA Compiler Framework for Floating-Point Algorithms, int. Conference on Field Programmable Logic and Applications (FPL 2005). Finland, 2005.
11. R. Mukherjee, A. Jones, P. Banerjee, System Level Synthesis of Multiple IP Blocks in the Behavioral Symthesis Tool, Int. Conf. on Parallel and Distributed Computing and Systems (PDCS), November 2003.