Low-power VLSI implementation of the inner receiver for OFDM-Based WLAN systems

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 55, Issue 2, 2008, Pages 672-686

  Troya, Alfonso ^a,b   Maharatna, Koushik ^a,c   Krstič, Miloš ^a   Grass, Eckhard ^a   Jagdhold, Ulrich ^a   Kraemer, Rolf ^a  

^a IHP   (Germany)

^b EUROPEAN PATENT OFFICE   (Netherlands)

^c UNIVERSITY OF SOUTHAMPTON   (United Kingdom)

Author keywords

Coordinate rotation digital computer (CORDIC); CORDIC; Fast Fourier transform (FFT); FFT; OFDM; Orthogonal frequency division multiplexing (OFDM); Wireless local area network (WLAN); WLAN

Indexed keywords

CHANNEL ESTIMATION; COMPUTER HARDWARE; DIGITAL COMPUTERS; ELECTRIC FILTERS; FAST FOURIER TRANSFORMS; INTEGRATED CIRCUIT LAYOUT; ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING; OSCILLATORS (ELECTRONIC); SIGNAL PROCESSING; SIGNAL RECEIVERS; WIRELESS LOCAL AREA NETWORKS (WLAN);

COORDINATE ROTATION DIGITAL COMPUTER; DECIMATION FILTER; DIGITAL BASEBAND PROCESSOR;

VLSI CIRCUITS;

EID: 42949142038     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2007.913732     Document Type: Article

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