A cordic like processor for computation of arctangent and absolute magnitude of a vector

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 2004, Pages

  Maharatna, Koushik ^a   Troya, Alfonso ^b   Krstić, Miloš ^b   Grass, Eckhard ^b   Jagdhold, Ulrich ^b  

^a UNIVERSITY OF BRISTOL   (United Kingdom)

^b IHP   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ALGORITHMS; DATABASE SYSTEMS; ERROR ANALYSIS; FORMAL LOGIC; ITERATIVE METHODS; MATHEMATICAL OPERATORS; OPTIMIZATION; VECTORS;

DOMAIN FOLDING; HARDWARE COMPLEXITY; PHASE ANGLE;

PROGRAM PROCESSORS;

EID: 4344667532     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. J. S. Walther, "A Unified Algorithm for Elementary Functions", Proc. Joint Spring Comput. Conf., vol. 38, pp. 379 - 385, Jul. 1971.
2. th IEEE International Symposium on Asynchronous Circuits and Systems, pp. 76 - 83, Manchester, U. K., April 2002.
3. K. Maharatna, A. S. Dhar and Swapna Banerjee, "A VLSI Array Architecture for Realization of DFT, DHT, DCT and DST", J. Signal Processing, vol. 81, pp. 1813 -1822, 2001.
4. M. Krstic, A. Troya, K. Maharatna and E. Grass, "Optimized Low-Power Synchronizer Design for the IEEE 802.11a Standard", Proc. ICASSP03, vol. II, pp. 321 -324.
5. H. Dawid and H. Meyr, "The Differential CORDIC Algorithms: Constant Scale Factor Redundant Implementation without Correcting Iterations", IEEE Trans. Comput., vol. 45, no. 3, pp. 307 - 318, 1996.
6. D. Timmermann and S. Dolling, "Unfolded Redundant CORDIC VLSI Architecture with Reduced Area and Power Consumption", http://www-md.e- technik.uni-rostock.de/ma/dtim/vlsi97.pdf