A single-chip 802.11a MAC/PHY with a 32-b RISC processor

IEEE Journal of Solid-State Circuits

Volumn 38, Issue 11, 2003, Pages 2001-2009

  Fujisawa, Toshio ^a   Hasegawa, Jun ^a   Tsuchie, Koji ^a   Shiozawa, Tatsuo ^a   Fujita, Tetsuya ^a   Saito, Toshitada ^a   Unekawa, Yasuo ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

Adaptive equalizers; Carrier sense multiaccess; Gain control; Orthogonal frequency division multiplexing; Signal processing; Wireless LAN

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRONICS PACKAGING; EQUALIZERS; GAIN CONTROL; INTEGRATED CIRCUIT MANUFACTURE; LOCAL AREA NETWORKS; ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING; STATIC RANDOM ACCESS STORAGE; TELECOMMUNICATION CONTROL; TRANSISTORS; WIRELESS TELECOMMUNICATION SYSTEMS;

ADAPTIVE EQUALIZERS; AUTOMATIC GAIN CONTROL CIRCUIT; CARRIER TO NOISE RATIO; MEDIUM ACCESS CONTROL; PHYSICAL LAYER; PLASTIC BALL GRID ARRAY; POWER SAVE POLL RESPONSE;

MICROPROCESSOR CHIPS;

EID: 0242468182     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.818135     Document Type: Article

References (4)

1. Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications, Sept. 1999.
2. Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications: High-Speed Physical Layer in the 5 GHz Band, Sept. 1999.
3. R. Ryan et al., "A single chip PHY COFDM modem for IEEE 802.11a with integrated ADC's and DAC's," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2001, pp. 338-339.
4. J. Thomson et al., "An integrated 802.11a baseband and MAC processor," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2002, pp. 126-127.