Optimized low-power synchronizer design for the IEEE 802.11a standard

ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

Volumn 2, Issue , 2003, Pages 333-336

  Krstić, Miloš ^a   Troya, Alfonso ^a   Maharatna, Koushik ^a   Grass, Eckhard ^a  

^a IHP   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (STANDARDS); MICROPROCESSOR CHIPS; SYNCHRONIZATION; TIMING CIRCUITS;

LOW POWER SYNCHRONIZERS;

ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING;

EID: 0141813376     PISSN: 15206149     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. IEEE P802.11a/07.0, Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: High Speed Physical Layer in the 5 GHz Band, Piscataway, NJ, 1999.
2. A. Troya, K. Maharatna, M. Krstic, E. Grass, R. Kraemer, "OFDM Synchronizer Implementation for an IEEE802.11a Compliant Modem", Proc. IASTED International Conference on Wireless and Optical Communications, Banff, Canada, pp. 152-157, July 2002.
3. Yun Chiu et al., OFDM Receiver Design, Final Report 12/12/2000. Downloaded from http://bwrc.eecs.berkeley.edu.
4. K. Maharatna, CORDIC based signal processors for biomedical applications, Ph.D. Dissertation, Jadavpur University, India, 2002.
5. E. Grass et al., "On the Single-Chip Implementation of a Hiperlan/2 and IEEE 802.11a Capable Modem", IEEE Personal Communications, vol. 8, no. 6, pp. 48-57, Dec. 2001.
6. th Int'l. OFDM Workshop, Hamburg, Germany, pp. 28.1 - 28.4, Sept. 2001.