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Volumn , Issue , 2007, Pages 147-150

Low temperature implementation of dopant-segregated band-edge metallic S/D junctions in thin-body SOI p-MOSFETs

Author keywords

[No Author keywords available]

Indexed keywords

BORON; BORON COMPOUNDS; NONMETALS; PLATINUM;

EID: 42449160921     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2007.4418886     Document Type: Conference Paper
Times cited : (55)

References (7)
  • 1
    • 29244432508 scopus 로고    scopus 로고
    • Integration of PtSi-based Schottky-Barrier p-MOSFETs with a Midgap Tungsten Gate
    • Dec
    • G. Larrieu, E. Dubois, "Integration of PtSi-based Schottky-Barrier p-MOSFETs with a Midgap Tungsten Gate"', IEEE Trans. Electron Devices, vol. 52, pp 2720-2726, Dec. 2005.
    • (2005) IEEE Trans. Electron Devices , vol.52 , pp. 2720-2726
    • Larrieu, G.1    Dubois, E.2
  • 2
    • 0042855935 scopus 로고    scopus 로고
    • Performance advantage of metal source/drain in ultra-thin-body silicon-on-insulator and dual-gate CMOS
    • Mar
    • D. Connelly, C. Faulkner, D. E. Grupp, "Performance advantage of metal source/drain in ultra-thin-body silicon-on-insulator and dual-gate CMOS", IEEE Trans. Electron Devices, vol. 50, pp 98-104, Mar. 2004.
    • (2004) IEEE Trans. Electron Devices , vol.50 , pp. 98-104
    • Connelly, D.1    Faulkner, C.2    Grupp, D.E.3
  • 4
    • 29244450764 scopus 로고    scopus 로고
    • High-performance 50-nm Gate Length Schottky Source Drain MOSFETs with Dopant-Segregation Junctions
    • A. Kinoshita, C. Tanaka, K. Uchida, J. Koga, "High-performance 50-nm Gate Length Schottky Source Drain MOSFETs with Dopant-Segregation Junctions", Symposium on VLSI Technology, pp 158-159, 2005.
    • (2005) Symposium on VLSI Technology , pp. 158-159
    • Kinoshita, A.1    Tanaka, C.2    Uchida, K.3    Koga, J.4
  • 5
    • 0030080749 scopus 로고    scopus 로고
    • Formation of cobalt silicided shallow junction using implant into/through silicide technology and low temperature furnace annealing
    • B. Chen, M. Chen, "Formation of cobalt silicided shallow junction using implant into/through silicide technology and low temperature furnace annealing", IEEE Trans. Electron Devices, vol. 43, pp 258-266, 1996.
    • (1996) IEEE Trans. Electron Devices , vol.43 , pp. 258-266
    • Chen, B.1    Chen, M.2
  • 6
    • 3142672426 scopus 로고    scopus 로고
    • Measurement of low Schottky barrier heights applied to S/D metal-oxide-semiconductor field effect transistors
    • Jul
    • Dubois, G. Larrieu, "Measurement of low Schottky barrier heights applied to S/D metal-oxide-semiconductor field effect transistors," J. Appl. Phys., vol. 96, no. 1, pp. 729-737, Jul. 2004.
    • (2004) J. Appl. Phys , vol.96 , Issue.1 , pp. 729-737
    • Dubois, G.L.1
  • 7
    • 50249155978 scopus 로고    scopus 로고
    • I. Post et al., A 65nm CMOS SOC Technology Featuring Strained Silicon Transistors for RF Applications IEDM Tech. Dig., December 2006.
    • I. Post et al., "A 65nm CMOS SOC Technology Featuring Strained Silicon Transistors for RF Applications IEDM Tech. Dig., December 2006.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.