Ultra low voltage operations in bulk CMOS logic circuits with dopant segregated schottky source/drain transistors

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2006, Pages

  Kinoshita, T ^a   Hasumi, R ^a   Hamaguchi, M ^a   Miyashita, K ^a   Komoda, T ^a   Kinoshita, A ^b   Koga, J ^b   Adachi, K ^b   Toyoshima, Y ^b   Nakayama, T ^a   Yamada, S ^a   Matsuoka, F ^a  

^a System LSI Division I   (Japan)

^b TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON DEVICES; LOGIC CIRCUITS; NETWORKS (CIRCUITS); SWITCHING CIRCUITS; SWITCHING THEORY; TRANSISTORS;

BULK CMOS; ENERGY-DELAY-PRODUCT; NAND GATES; PROPAGATION DELAYS; SCHOTTKY; SCHOTTKY SOURCE/DRAIN; ULTRA LOW POWER; ULTRA-LOW-VOLTAGE;

DECISION SUPPORT SYSTEMS;

EID: 46049105349     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2006.346961     Document Type: Conference Paper

References (3)

1. A. Kinoshita, C. Tanaka, K. Uchida and J. Koga, "High-performance 50-nm-gate-length Schottky-source/srain MOSFETs with dopant-segregation junctions" 2005 Symp. VLSI Tech, pp. 158-159
2. C.H. Ko, H.W. Chen, T.J. Wang, T.M. Kuan, J.W. Hsu, C.Y. Huang, C.H Ge, L.S. Lai, and W.C. Lee, "NiSi Schottky barrier process-strained Si (SBPSS) CMOS technology for high performance applications" 2006 Symp. VLSI Tech., pp. 98-99
3. A. Kinoshita, T. Kinoshita, T. Nishi, K. Uchida, S. Toriyama, R. Hasumi and J. Koga, "Comprehensive study on injection velocity enhancement in dopant-segregated Schottky MOSFETs" 2006 IEDM. in press