Low-jitter multi-phase clock generation: A comparison between DLLs and shift registers

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2007, Pages 2854-2857

  Gao, Xiang ^a   Klumperink, Eric A M ^a   Nauta, Bram ^a  

^a UNIVERSITY OF TWENTE   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC CIRCUITS; PHASE LOCKED LOOPS; SHIFT REGISTERS; TIME DELAY; WHITE NOISE;

CURRENT MODE LOGIC (CML); DELAY LOCKED LOOP (DLL); MULTI PHASE CLOCK GENERATOR (MPCG);

TIMING JITTER;

EID: 34548835501     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2007.378767     Document Type: Conference Paper

References (10)

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