Impact of process scaling on the efficacy of leakage reduction schemes

2004 International Conference on Integrated Circuit Design and Technology, ICICDT

Volumn , Issue , 2004, Pages 3-11

  Tsai, Yuh Fang ^b   Duarte, David ^a   Vijaykrishnan, N ^b   Irwin, Mary Jane ^b  

^a INTEL CORPORATION   (United States)

^b PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

Leakage reduction; Low power; Process variations; Technology scaling

Indexed keywords

LEAKAGE REDUCTION; LOW POWER; PROCESS VARIATIONS; TECHNOLOGY SCALING;

CMOS INTEGRATED CIRCUITS; DATA STORAGE EQUIPMENT; DIELECTRIC MATERIALS; GATES (TRANSISTOR); MICROPROCESSOR CHIPS; MODIFICATION; MOS CAPACITORS; OPTIMIZATION; THRESHOLD VOLTAGE;

LEAKAGE CURRENTS;

EID: 4143094905     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

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