-
3
-
-
14244267096
-
Hardware Synthesis from Term Rewriting Systems
-
99 Lisbon, Portugal, December
-
J. C. Hoe and Arvind, "Hardware Synthesis from Term Rewriting Systems," Proceeding of VLSI'99 Lisbon, Portugal, December 1999.
-
(1999)
Proceeding of VLSI
-
-
Hoe, J.C.1
Arvind2
-
6
-
-
0031703213
-
A Power Management Methodology for High-Level Synthesis
-
January
-
G. Lakshminarayana, A. Raghunathan, N. K. Jha, and S. Dey, "A Power Management Methodology for High-Level Synthesis," International Conference on VLSI Design, pp. 24-29, January 1998.
-
(1998)
International Conference on VLSI Design
, pp. 24-29
-
-
Lakshminarayana, G.1
Raghunathan, A.2
Jha, N.K.3
Dey, S.4
-
7
-
-
40949142524
-
Background
-
Kluwer Academic Publishers
-
A. Raghunathan, N. K.Jha, and S. Dey, "Background," in High-Level Power Analysis And Optimization. Kluwer Academic Publishers, 1998, pp. 18-21.
-
(1998)
High-Level Power Analysis And Optimization
, pp. 18-21
-
-
Raghunathan, A.1
Jha, N.K.2
Dey, S.3
-
8
-
-
40949102431
-
Algorithms for Low Power Hardware Synthesis from CAOS - Concurrent Action Oriented Specifications,
-
No.2006-03, 2006
-
G. Singh and S. K. Shukla, "Algorithms for Low Power Hardware Synthesis from CAOS - Concurrent Action Oriented Specifications," FERMAT Technical Report No.2006-03, 2006.
-
FERMAT Technical Report
-
-
Singh, G.1
Shukla, S.K.2
-
10
-
-
0033683172
-
-
W. T. Shiue, High level synthesis for peak power minimization using ilp, In Proceedings of the IEEE International Conference on ASSAP, pp. 103-112, 2000.
-
W. T. Shiue, "High level synthesis for peak power minimization using ilp," In Proceedings of the IEEE International Conference on ASSAP, pp. 103-112, 2000.
-
-
-
-
11
-
-
0029710305
-
Scheduling techniques to enable power management
-
June
-
J.Monteiro, S.Devadas, P.Ashar, and A.Mauskar, "Scheduling techniques to enable power management," Proceedings of Design Automatin Conference, pp. 349-352, June 1996.
-
(1996)
Proceedings of Design Automatin Conference
, pp. 349-352
-
-
Monteiro, J.1
Devadas, S.2
Ashar, P.3
Mauskar, A.4
-
12
-
-
0030713556
-
Power Management techniques for Control-flow intensive designs
-
June
-
A. Raghunathan, S. Dey, N. Jha, and K.Wakabayashi, "Power Management techniques for Control-flow intensive designs," Proceedings of Design Automation Conference, no. 429-434, June 1997.
-
(1997)
Proceedings of Design Automation Conference
, Issue.429-434
-
-
Raghunathan, A.1
Dey, S.2
Jha, N.3
Wakabayashi, K.4
-
13
-
-
0033332247
-
High-Level Synthesis Of Low Power Control-Flow Intensive Circuits
-
December
-
K. S. Khouri, G. Lakshminarayana, and N. K. Jha, "High-Level Synthesis Of Low Power Control-Flow Intensive Circuits," IEEE Transactions on Computer-Aided Design (TCAD'99), vol. 18, December 1999.
-
(1999)
IEEE Transactions on Computer-Aided Design (TCAD'99)
, vol.18
-
-
Khouri, K.S.1
Lakshminarayana, G.2
Jha, N.K.3
-
14
-
-
0035208946
-
Transient Power Management Through High Level Synthesis
-
V. Raghunathan, S. Ravi, A. Raghunathan, and G. Lakshminarayana, "Transient Power Management Through High Level Synthesis," In Proceedings of the ICCAD, pp. 545-552, 2001.
-
(2001)
In Proceedings of the ICCAD
, pp. 545-552
-
-
Raghunathan, V.1
Ravi, S.2
Raghunathan, A.3
Lakshminarayana, G.4
-
15
-
-
0038453474
-
-
S. P. Mohanty and N. Ranganathan, A framework for energy and transient power reduction during behavioral synthesis, In Proceedings of the International Conference on VLSI Design, pp. 539-545, 2003.
-
S. P. Mohanty and N. Ranganathan, "A framework for energy and transient power reduction during behavioral synthesis," In Proceedings of the International Conference on VLSI Design, pp. 539-545, 2003.
-
-
-
-
16
-
-
0033684369
-
Low-Power Scheduling with Resources Operating at Multiple Voltages
-
June
-
W.-T. Shiue and C. Chakrabarti, "Low-Power Scheduling with Resources Operating at Multiple Voltages," IEEE Transactions On Circuits and Systems - II: Analog and Digital Signal Processing, vol. 47, no. 6, pp. 536-543, June 2000.
-
(2000)
IEEE Transactions On Circuits and Systems - II: Analog and Digital Signal Processing
, vol.47
, Issue.6
, pp. 536-543
-
-
Shiue, W.-T.1
Chakrabarti, C.2
-
17
-
-
18244423483
-
Multiple Voltage-based Scheduling Methodology for Low-power in the High-level Synthesis
-
June
-
A. Kumar and M. Bayoumi, "Multiple Voltage-based Scheduling Methodology for Low-power in the High-level Synthesis," IEEE International Symposium on Circuits and Systems, vol. 1, pp. 371-374, June 1999.
-
(1999)
IEEE International Symposium on Circuits and Systems
, vol.1
, pp. 371-374
-
-
Kumar, A.1
Bayoumi, M.2
|