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Volumn , Issue , 2006, Pages 49-58

Low-power hardware synthesis from TRS-based specifications

Author keywords

[No Author keywords available]

Indexed keywords

CONCURRENT ACTION ORIENTED SPECIFICATIONS (CAOS); HARDWARE DESIGNS; HARDWARE SYNTHESIS;

EID: 40949118859     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (7)

References (17)
  • 3
    • 14244267096 scopus 로고    scopus 로고
    • Hardware Synthesis from Term Rewriting Systems
    • 99 Lisbon, Portugal, December
    • J. C. Hoe and Arvind, "Hardware Synthesis from Term Rewriting Systems," Proceeding of VLSI'99 Lisbon, Portugal, December 1999.
    • (1999) Proceeding of VLSI
    • Hoe, J.C.1    Arvind2
  • 8
    • 40949102431 scopus 로고    scopus 로고
    • Algorithms for Low Power Hardware Synthesis from CAOS - Concurrent Action Oriented Specifications,
    • No.2006-03, 2006
    • G. Singh and S. K. Shukla, "Algorithms for Low Power Hardware Synthesis from CAOS - Concurrent Action Oriented Specifications," FERMAT Technical Report No.2006-03, 2006.
    • FERMAT Technical Report
    • Singh, G.1    Shukla, S.K.2
  • 10
    • 0033683172 scopus 로고    scopus 로고
    • W. T. Shiue, High level synthesis for peak power minimization using ilp, In Proceedings of the IEEE International Conference on ASSAP, pp. 103-112, 2000.
    • W. T. Shiue, "High level synthesis for peak power minimization using ilp," In Proceedings of the IEEE International Conference on ASSAP, pp. 103-112, 2000.
  • 15
    • 0038453474 scopus 로고    scopus 로고
    • S. P. Mohanty and N. Ranganathan, A framework for energy and transient power reduction during behavioral synthesis, In Proceedings of the International Conference on VLSI Design, pp. 539-545, 2003.
    • S. P. Mohanty and N. Ranganathan, "A framework for energy and transient power reduction during behavioral synthesis," In Proceedings of the International Conference on VLSI Design, pp. 539-545, 2003.
  • 17
    • 18244423483 scopus 로고    scopus 로고
    • Multiple Voltage-based Scheduling Methodology for Low-power in the High-level Synthesis
    • June
    • A. Kumar and M. Bayoumi, "Multiple Voltage-based Scheduling Methodology for Low-power in the High-level Synthesis," IEEE International Symposium on Circuits and Systems, vol. 1, pp. 371-374, June 1999.
    • (1999) IEEE International Symposium on Circuits and Systems , vol.1 , pp. 371-374
    • Kumar, A.1    Bayoumi, M.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.