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3
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Integrated cluster bus performance for the IBM S/390 parallel sysplex
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C. L. Rao, G. M. King, and B. A. Weiler, "Integrated Cluster Bus Performance for the IBM S/390 Parallel Sysplex," IBM J. Res. & Dev. 43, No. 5/6, 855-862 (September/November 1999).
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Self-timed interface of the input/output subsystem of the IBM eServer z900
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J. M. Hoke, P. W. Bond, R. R. Livolsi, T. C. Lo, F. S. Pidala, and G. Steinbrueck, "Self-Timed Interface of the Input/Output Subsystem of the IBM eServer z900," IBM J. Res. & Dev. 46, No. 4/5, 447-460 (July/September 2002).
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J. Darringer, E. Davidson, D. Hathaway, B. Koenemann, M. Lavin, B. Lee, J. Morrell, S. Ponnapalli, K. Rahmat, W. Roesner, E. Schanzenbach, and L. Trevillyan, "EDA in IBM: Past, Present and Future," IEEE Trans. Computer-Aided Design, Integrated Circuits & Syst. 19, 1476-1497 (December 2000).
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B. Wile, M. P. Mullen, C. Hanson, D. G. Bair, K. M. Lasko, P. J. Duffy, E. J. Kaminski, Jr., T. E. Gilbert, S. M. Licker, R. G. Sheldon, W. D. Wollyung, W. J. Lewis, and R. J. Adkins, "Functional Verification of the CMOS S/390 Parallel Enterprise Server G4 System," IBM J. Res. & Dev. 41, No. 4/5, 549-566 (July/September 1997).
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7
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more..
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Test methodologies and design automation for IBM ASICs
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L. Stok, D. S. Kung, D. Brand, A. D. Drumm, A. J. Sullivan, L. N. Reddy, N. Hieter, D. J. Geiger, H. H. Chao, and P. J. Osler, "BooleDozer: Logic Synthesis for ASICs," IBM J. Res. & Dev. 40, No. 4, 407-430 (July 1996).
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11
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0033325635
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PLL modeling and verification in a cycle-simulation environment
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G. A. Van Huben, T. G. McNamara, and T. E. Gilbert, "PLL Modeling and Verification in a Cycle-Simulation Environment," IBM J. Res. & Dev. 43, No. 5/6, 915-925 (September/November 1999).
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SimAPI - A common programming interface for simulation
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G. G. Hallock, E. J. Kaminski, Jr., K. M. Lasko, and M. P. Mullen, "SimAPI - A Common Programming Interface for Simulation," IBM J. Res. & Dev. 41, No. 4/5, 601-610 (July/September 1997).
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J. Silverio, H. Kumar, S. Joseph, and B. Hoppe, "Method for Verification of Various Asynchronous Frequency Domains in a STI Switch Chip, by Implementing a Greatest Common Factor Mathematical Approach to Generate the Discrete Simulation Cycle Values and Randomly Select the Simulation Cycle Percent Variation Across the Multiple Domains," patent filed 2003.
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Silverio, J.1
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