The structure of chips and links comprising the IBM eServer z990 I/O subsystem

IBM Journal of Research and Development

Volumn 48, Issue 3-4, 2004, Pages 449-459

  Chencinski, Edward W ^a   Becht, Michael J ^a   Bubb, Tim E ^a   Burwick, Carolynn G ^a   Haess, Juergen ^b   Helms, Markus M ^b   Hoke, Joseph M ^a   Schlipf, Thomas ^b   Turner, Jeffrey M ^a   Ulland, Hartmut ^b   Walz, Manfred H ^b   Whitehead, Carl H ^a   Zilles, Gerhard ^b  

^a IBM   (United States)

^b IBM   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CACHE MEMORY; INPUT OUTPUT PROGRAMS; INTERFACES (COMPUTER); MICROPROCESSOR CHIPS; SERVERS;

CENTRAL ELECTRONIC COMPLEX; MEMORY BUS ADAPTER; SELF TIMED INTERFACE;

MULTIPROCESSING SYSTEMS;

EID: 4043053845     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.483.0449     Document Type: Article

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