Functional verification of the CMOS S/390 Parallel Enterprise Server G4 system

IBM Journal of Research and Development

Volumn 41, Issue 4-5, 1997, Pages 549-564

  Wile, B ^a   Mullen, M P ^a   Hanson, C ^a   Bair, D G ^a   Lasko, K M ^a   Duffy, P J ^a   Kaminski Jr , E J ^a   Gilbert, T E ^a   Licker, S M ^a   Sheldon, R G ^a   Wollyung, W D ^a   Lewis, W J ^a   Adkins, R J ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE DESCRIPTION LANGUAGES; CONSTRAINT THEORY; INPUT OUTPUT PROGRAMS; LOGIC DESIGN; PARALLEL PROCESSING SYSTEMS; SWITCHING NETWORKS;

BUS SWITCHING NETWORK (BSN); FUNCTIONAL VERIFICATION; MEMORY BUS ADAPTORS (MBA); SYMMETRIC MULTIPROCESSOR (SMP);

MICROPROCESSOR CHIPS;

EID: 0031176666     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.414.0549     Document Type: Article

References (9)

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