Characterization and modeling of CMOS on-chip coupled interconnects

ESSDERC 2007 - Proceedings of the 37th European Solid-State Device Research Conference

Volumn 2007, Issue , 2007, Pages 159-162

  Kumar, Rakesh ^a   Rustagi, Subhash C ^a   Kang, Kai ^a   Mouthaan, K ^b   Wong, T K S ^c  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^c NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CHIP SCALE PACKAGES; ELECTRIC LINES; INDUCTANCE; INTERCONNECTION NETWORKS; SCATTERING PARAMETERS; SUBSTRATES;

COUPLED INTERCONNECTS; COUPLED LINES; MODEL PARAMETERS;

CMOS INTEGRATED CIRCUITS;

EID: 39549105793     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2007.4430903     Document Type: Conference Paper

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