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Volumn , Issue , 2006, Pages 313-316

A 0.13 μm low-power race-free programmable logic array

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER UTILIZATION; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; LOGIC GATES; PROGRAMMABLE LOGIC CONTROLLERS;

EID: 39049095143     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2006.320899     Document Type: Conference Paper
Times cited : (2)

References (7)
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    • International Technology Roadmap for Semiconductors, [online].
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  • 4
    • 0035311079 scopus 로고    scopus 로고
    • Power: A First-Class Architectural Design Constraint
    • Apr
    • T. Mudge, "Power: A First-Class Architectural Design Constraint," Computer, 34, pp. 52-58, Apr. 2001.
    • (2001) Computer , vol.34 , pp. 52-58
    • Mudge, T.1
  • 5
    • 28244471705 scopus 로고    scopus 로고
    • The Circuits and Physical Design of the Synergistic Processor Element of a CELL Processor
    • O.Takahashi et al., "The Circuits and Physical Design of the Synergistic Processor Element of a CELL Processor," VLSI Cir. Symp. Tech. Digest, pp. 20-23, 2005.
    • (2005) VLSI Cir. Symp. Tech. Digest , pp. 20-23
    • Takahashi, O.1
  • 6
    • 0035429464 scopus 로고    scopus 로고
    • Analysis and Design of High-Speed and Low-Power CMOS PLAs
    • Aug
    • J. Wang, C. Chang, and C.Yeh, "Analysis and Design of High-Speed and Low-Power CMOS PLAs," IEEE J. Solid-State Circuits, 36, no.8, pp. 1250-1262, Aug. 2001.
    • (2001) IEEE J. Solid-State Circuits , vol.36 , Issue.8 , pp. 1250-1262
    • Wang, J.1    Chang, C.2    Yeh, C.3
  • 7
    • 0036565318 scopus 로고    scopus 로고
    • A sub-130 nm conditional keeper technique
    • May
    • A. Alvandpour et al., "A sub-130 nm conditional keeper technique," IEEE J. Solid-State Circuits, 37, no.5, pp. 633-638, May 2002.
    • (2002) IEEE J. Solid-State Circuits , vol.37 , Issue.5 , pp. 633-638
    • Alvandpour, A.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.