Design-for-manufacture for multigate oxide CMOS process

IEEE Transactions on Semiconductor Manufacturing

Volumn 21, Issue 1, 2008, Pages 41-44

  Lin, Qi ^a,b   Mei, Ma ^b   Vo, Tony ^b   Fan, Jenny ^b   Wu, Xin ^a,b   Li, Richard ^a,b   Li, Xiao Yu ^a,b  

^a IEEE

^b XILINX INC   (United States)

Author keywords

Design for manufacture (DFM); Field programmable gate array (FPGA); Layout; Multigate oxide

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; OXIDES;

DESIGN-FOR-MANUFACTURE (DFM); ETCHING PROCESS; MULTIGATE OXIDES; MULTIOXIDE PRODUCT MANUFACTURE;

CMOS INTEGRATED CIRCUITS;

EID: 38949158011     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2007.913190     Document Type: Conference Paper

References (5)

1. X. Dong, I. Seo, and W. Kao, "New metal fill consideration for nanometer technologies," in Proc. IEEE 6th Int. Conf. ASIC, Oct. 2005, pp. 802-805.
2. F. Schellenberg, "Design for manufacturing in the semiconductor industry: The litho/design workshop," in Proc. IEEE 12th Int. Conf. VLSI Design, Jan. 1999, pp. 111-119.
3. P. Yu, S. Shi, and D. Pan, "Process variation aware OPC with variational lithography modeling," in Proc. IEEE 43rd Design Automation Conf., Jul. 2006, pp. 785-790.
4. K. Cox, M. Chonko, C. Honcik, and S. VanDyke, "The effect of HF processing on gate oxide degradation in aggressive poly buffered LOCOS isolation," IEEE Electron Device Lett., vol. 17, no. 2, pp. 50-52, Feb. 1996.
5. T. Suzuki, H. Kunishima, T. Wake, and S. Chikaki, "High controllability and low coast APM process by one-bath type wet-bench for multi gate oxide pre-cleaning," in Proc. IEEE 9th Int. Symp. Semiconductor Manufacture, Sep. 2000, pp. 321-324.