New metal fill considerations for nanometer technologies

ASICON 2005: 2005 6th International Conference on ASIC, Proceedings

Volumn 2, Issue , 2005, Pages 804-807

  Dong, Xiaopeng ^a   Seo, Inhwan ^a   Kao, William ^a  

^a CADENCE DESIGN SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP TIMING; METAL DENSITY VERIFICATION; METAL FILL TRIMMING; POWER STRAPPING;

FILLER METALS; INTERCONNECTION NETWORKS; NANOTECHNOLOGY; SEMICONDUCTOR DEVICE MANUFACTURE;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 33847252094     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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7. Y.Chen, P.Gupta, and A.B.Kahng, "Performance-impact limited area fill synthesis," Proc. of DAC, pp.22-27, 2003.