A power optimized continuous-time ΔΣ ADC for audio applications

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 2, 2008, Pages 351-360

  Pavan, Shanthi ^a   Krishnapura, Nagendra ^a   Pandarinathan, Ramalingam ^a   Sankar, Prabu ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY MADRAS   (India)

Author keywords

Analog to digital converter (ADC); Continuous time; Data converter; Jitter; Oversampling; Sigma delta modulation

Indexed keywords

ANALOG TO DIGITAL CONVERSION; BANDWIDTH; CMOS INTEGRATED CIRCUITS; ENERGY DISSIPATION; OPTIMIZATION;

AUDIO MODULATOR; CIRCUIT DESIGN; EXCESS DELAY COMPENSATION;

MODULATORS;

EID: 38849127433     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.914263     Document Type: Article

References (16)

1. S. Norsworthy, R. Schreier, and G. Temes, Delta-Sigma Data Converters: Theory, Design, and Simulation. New York: IEEE Press, 1996.
2. F. Gerfers, M. Ortmanns, and Y. Manoli, "A 1.5-V 12-bit power-efficient continuous-time third-order ΣΔ modulator," IEEE J. Solid-State Circuits, vol. 38, no. 8, pp. 1343-1352, Aug. 2003.
3. M. Ortmanns, Y. Manoli, and F. Gerfers, "A continuous-time sigma-delta modulator with reduced jitter sensitivity," in Proc. Eur. Solid-State Circuits Conf., 2002, pp. 287-290.
4. B. Baggini, P. Basedau, R. Becker, P. Bode, R. Burdenski, F. Esfahani, W. Groeneweg, M. Helfenstein, A. Lampe, R. Ryter, and R. Stephan, "Baseband and audio mixed-signal front-end IC for GSM/EDGE applications," IEEE J. Solid-State Circuits, vol. 4.1, no. 6, pp. 1364-1379, Jun. 2006.
5. K. Nguyen, R. Adams, K. Sweetland, and H. Chen, "A 106-dB SNR hybrid oversampling analog-to-digital converter for digital audio," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2408-2415, Dec. 2005.
6. L. Dorrer, F. Kuttner, A. Santner, C. Kropf, T. Hartig, P. Torta, and P. Greco, "A 2.2 mW, continuous-time sigma-delta ADC for voice coding with 95 dB dynamic range in a 65 nm CMOS process," in Proc. Eur. Solid-State Circuits Conf., 2006, pp. 195-198.
7. S. Pavan, N. Krishnapura, R. Pandarinathan, and P. Sankar, "A 90 μW 15-bit delta-sigma ADC for digital audio," in Proc. Eur. Solid-State Circuits Conf., 2007, pp. 198-201.
8. W. Lee, "A novel higher-order interpolative modulator topology for high resolution oversampling A/D converters," Master's thesis, Mass. Inst. of Technol., Cambridge, MA, 1987.
9. J. Cherry and W. Snelgrove, "Clock jitter and quantizer metastability in continuous-time delta-sigma modulators," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 46, no. 6, pp. 661-676, Jun. 1999.
10. O. Oliaei, "Clock jitter noise spectra in continuous-time delta-sigma modulators," in Proc. IEEE Int. Symp. Circuits Syst., 1999, vol. 2, pp. 192-195.
11. L. Hernandez, A. Wiesbauer, S. Paton, and A. D. Giandomencio, "Modelling and optimization of low pass continuous-time sigma delta modulators for clock jitter noise reduction," in Proc. Int. Symp. Circuits Syst., 2004, vol. 1, pp. 1072-1075.
12. K. Reddy and S. Pavan, "Fundamental limitations of continuous-time sigma delta modulators due to clock jitter," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 10, pp. 2184-2194, Oct. 2007.
13. S. Rabii and B. Wooley, "A 1.8-V digital-audio sigma-delta modulator in 0.8-μm CMOS," IEEE J. Solid-State Circuits, vol. 32, no. 6, pp. 783-796, Jun. 1997.
14. P. Sankar and S. Pavan, "Analysis of integrator nonlinearity in a class of continuous-time delta-sigma modulators," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 12, pp. 1125-1129, Dec. 2007.
15. R. Baird and T. Fiez, "Linearity enhancement of multibit ΔΣ A/D and D/A converters using data weighted averaging," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 42, no. 12, pp. 753-762, Dec. 1995.
16. E. van der Zwan and E. Dijkmans, "A 0.2-mW CMOS ΣΔ modulator for speech coding with 80 dB dynamic range," IEEE J. Solid-State Circuits, vol. 31, no. 12, pp. 1873-1880, Dec. 1996.