Modelling and optimization of low pass continuous-time sigma-delta modulators for clock jitter noise reduction

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 2004, Pages

  Hernandez L ^a   Wiesbauer, A ^b   Paton S ^a   Di Giandomenico, A ^b  

^a UNIVERSIDAD CARLOS III DE MADRID   (Spain)

^b INFINEON TECHNOLOGIES AUSTRIA AG   (Austria)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; JITTER; MATHEMATICAL MODELS; SIGNAL TO NOISE RATIO; SPURIOUS SIGNAL NOISE; VECTOR QUANTIZATION;

CLOCK JITTER; JITTER SENSITIVITY; LOOP DELAY;

DELTA SIGMA MODULATION;

EID: 4344640048     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. J.A. Cherry, and W.M. Snelgrove "Continuous-Time Delta-Sigma Modulators for High-Speed A/D Conversion", Kluwer Academic Publishers, Boston, MA, 1999
2. A. Di Giandomenico, S. Patón, A. Wiesbauer, L. Hernández, T. Pötscher and L. Dörrer. "A 15 MHz Bandwidth Sigma-Delta ADC with 11 Bits Resolution in 0.13μm CMOS", ESSCIRC 2003, European Solid-State Circuit Conference,2003
3. P, Malcovati, S. Brigati, F. Francesconi, F. Maloberti, P. Cusinato and A. Baschirotto. "Behavioral modeling of switched-capacitor sigma-delta modulators" IEEE Trans. on Circuits and Systems I, Vol. 50, pp. 352-364, March 2003