A 20 Gb/s 1:4 DEMUX without inductors and low-power divide-by-2 circuit in 0.13 μm CMOS technology

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 2, 2008, Pages 541-548

  Kim, Byung Guk ^a,b   Kim, Lee Sup ^a,b   Byun, Sangjin ^a,c   Yu, Hyun Kyu ^a,c  

^a IEEE

^b Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^c Electronics and Telecommunications Research Institute (ETRI)   (South Korea)

Author keywords

CMOS; Delay locked loop (DLL); DEMUX; Latch; Static frequency divider

Indexed keywords

BANDWIDTH; ELECTRIC POWER UTILIZATION; PHASE LOCKED LOOPS; SIGNAL ANALYSIS;

BUFFER INSERTION; STATIC FREQUENCY DIVIDER;

CMOS INTEGRATED CIRCUITS;

EID: 38849085785     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.914332     Document Type: Article

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