A redundant multivalued logic for a 10-gb/s cmos demultiplexer ic

IEEE Journal of Solid-State Circuits

Volumn 38, Issue 1, 2003, Pages 107-113

  Tanabe, Akira ^a   Nakahara, Yasushi ^a   Furukawa, Akio ^a   Mogami, Tohru ^a  

^a NEC CORPORATION   (Japan)

Author keywords

CMOS ICs; Demultiplexing; Multivalued logic; Optical communication; Redundancy

Indexed keywords

CMOS INTEGRATED CIRCUITS; DEMULTIPLEXING; ELECTRIC POTENTIAL; FLIP FLOP CIRCUITS; LOGIC CIRCUITS; MOSFET DEVICES; OPTICAL COMMUNICATION; REDUNDANCY;

CONVENTIONAL OVERSAMPLING METHOD; DEMULTIPLEXERS; MOS CURRENT MODE LOGIC;

MANY VALUED LOGICS;

EID: 0037249015     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2002.806287     Document Type: Article

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